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Coursera - VLSI CAD: Logic to Layout (University of Illinois)
WEBRip | English | MP4 | 960 x 540 | AVC ~63.6 kbps | 29.970 fps
AAC | 128 Kbps | 44.1 KHz | 2 channels | Subs: English (.srt) | ~17 hours | 1.33 GB
Genre: eLearning Video / Computer Engineering, CAD
A modern VLSI chip has a zillion parts - logic, control, memory, interconnect, etc. How do we design these complex chips? Answer: CAD software tools. Learn how to build these tools in this class.

Content:

01 Orientation
02 Welcome and Introduction Week 1
03 Computational Boolean Algebra Week 1
04 BDDs SAT Week 2
05 2-Level Synthesis Algebraic Division Week 3
06 Multilevel Factor Extract Dont Cares Week 4
07 ASIC Placement Week 5
08 Technology Mapping Week 6
09 ASIC Routing Week 7
10 Timing Analysis Week 8
11 Tools

General
Complete name : 07_8.4-_Logic_Synthesis_-_Controllability_Dont_Cares_19-59.mp4
Format : MPEG-4
Format profile : Base Media
Codec ID : isom
File size : 28.7 MiB
Duration : 19mn 59s
Overall bit rate : 201 Kbps
Writing application : Lavf55.10.100

Video
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Format : AVC
Format/Info : Advanced Video Codec
Format profile : [email protected]
Format settings, CABAC : Yes
Format settings, ReFrames : 4 frames
Codec ID : avc1
Codec ID/Info : Advanced Video Coding
Duration : 19mn 59s
Bit rate : 63.6 Kbps
Width : 960 pixels
Height : 540 pixels
Display aspect ratio : 16:9
Frame rate mode : Constant
Frame rate : 29.970 fps
Color space : YUV
Chroma subsampling : 4:2:0
Bit depth : 8 bits
Scan type : Progressive
Bits/(Pixel*Frame) : 0.004
Stream size : 9.09 MiB (32%)
Writing library : x264 core 129 r2230 1cffe9f
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Audio
ID : 2
Format : AAC
Format/Info : Advanced Audio Codec
Format profile : LC
Codec ID : 40
Duration : 19mn 59s
Bit rate mode : Constant
Bit rate : 128 Kbps
Channel(s) : 2 channels
Channel positions : Front: L R
Sampling rate : 44.1 KHz
Compression mode : Lossy
Delay relative to video : -800ms
Stream size : 18.4 MiB (64%)

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